The present invention relates generally to the field of integrated circuits and in particular to a system and method to synchronize an output signal generated by a integrated circuit component to an applied clock signal.
Synchronous logic refers to a wide array of analog and digital circuits wherein state—the collective contents of storage locations and the conditions of input and output signals—changes in temporal synchronicity with an applied periodic signal, known in the art as a clock signal. Particularly in systems comprising a plurality of interconnected integrated circuits, synchronizing the state transition of certain output signals to an applied clock input is important to reduce clock skew and achieve reliable high frequency operation. One example of a synchronous integrated circuit component commonly interconnected to other high-frequency, synchronous circuits is SDRAM memory.
A Synchronous Dynamic Random Access Memory (SDRAM) component is a high-density, solid-state, volatile, digital data storage device. As its name implies, a SDRAM differs from a DRAM in that applied control signals, output timing signals, and data bits (in both read and write directions) transition synchronously with an applied clock signal. This feature simplifies the control of the SDRAM by processors, memory controllers, bus interface circuits, and other synchronous, or clocked, circuits, and allows for higher operating frequencies than conventional DRAMs. Tight synchronization with a clock input is even more critical for Double Data Rate (DDR) SDRAM components, which provide data and control signal transitions on both edges of the clock signal.
One example of a synchronous SDRAM signal is a data strobe signal, which is used in at least SDRAM write and read operations. The data strobe signal is provided as an input to the SDRAM when writing data to it, and is used by the SDRAM to latch write data synchronously with the clock signal. Conversely, the data strobe signal is an output generated by the SDRAM when data is read from it, and is used by memory controllers to latch read data synchronously with the clock signal.
During read operations, the SDRAM generates the data strobe signal synchronously with the clock signal. Ideally, the data bits (DQ) and data strobe (DQS) exhibit little or no skew relative to the applied clock signal (CK). The degree to which DQ and DQS diverge from synchronicity with the CK limits high frequency operation, and is specified by SDRAM manufacturers as tAC and tDQSCK, respectively. One challenge of SDRAM design, manufacture, and testing is to minimize tAC and tDQSCK.
A conventional approach to reducing the skew between synchronous output signals and the clock signal in an integrated circuit is the use of a Delay Locked Loop (DLL). A DLL dynamically adjusts the delay of a variable delay line to reduce the phase skew between a synchronous signal being generated and the clock signal. DLLs reduce skew between on-chip, or internal, signals.
To reduce the skew between corresponding external signals—such as the applied CK input and the DQS output during read operations—it is known to add a trimmable feedback delay to a DLL that accounts for input and output buffer delay. This trimmable delay may be altered during manufacturing testing by monitoring the external signals in a tester and blowing one or more fuses associated with delay elements in the feedback delay circuit until the external signals are phase aligned. Since it consumes valuable testing time, this procedure is performed on a selected number of SDRAM components on a wafer and the resultant values of the feedback delays are averaged. Fuses are then blown on the remaining SDRAM components on the wafer to set the feedback delay of each to this average value.
However, due to process variations, the delays imposed by input and output buffers may vary widely, even among SDRAM components on the same wafer. Consequently, each setting the feedback delay in each SDRAM component to the average value means that the SDRAM components are not individually optimized to minimize the phase skew between synchronous outputs and the clock signal.